As silicon technologies move into the nanometer regime, there is growing concern for the reliability of transistor devices. Device scaling may aggravate a number of long standing silicon failure mechanisms, and it may introduce a number of new non-trivial failure modes. Unless these reliability concerns are addressed, component yield and lifetime may soon be compromised.
The following list highlights certain silicon faults.
Device Wear-Out—Metal electro-migration and hot carrier degradation are traditional mechanisms that lead to eventual device failure. While these mechanisms continue to be a problem for deep-submicron silicon, new concerns arise due to the extremely thin gate oxides utilized in current and future process technologies, which lead to gate oxide wear-out (or time dependent dielectric breakdown). Over time, gate oxides can break and become conductive, essentially shorting the transistor and rendering it useless. Fast clocks, high temperatures, and voltage scaling limitations are well-established architectural trends that conspire to aggravate this failure mode.
Transistor Infant Mortality—Extreme device scaling also exacerbates early transistor failures, due to weak transistors that escape post-manufacturing testing. These weak transistors work initially, but they have dimensional and doping deficiencies that subject them to much higher stress than normal. Quickly (within days to months from deployment) they break down and render the device unusable. Traditionally, early transistor failures have been addressed with aggressive burn-in testing, where, before being placed in the field, devices are subjected to high voltage and temperature testing, to accelerate the failure of weak transistors. Those that survive this grueling birth are likely to be robust devices, thereby ensuring a long product lifetime. In the deep-submicron regime, burn-in becomes less effective as devices are subject to thermal run-away effects, where increased temperature leads to increased leakage current, which in turn leads to yet higher temperatures and further increases in leakage current. The end result is that aggressive burn-in can destroy even robust devices. Manufacturers may be forced to either sacrifice yield with an aggressive burn-in or experience more frequent early transistor failures in the field.
Manufacturing Defects that Escape Testing—Optical proximity effects, airborne impurities, and processing material defects can all lead to the manufacturing of faulty transistors and interconnect. Moreover, deep-submicron gate oxides have become so thin that manufacturing variation can lead to currents penetrating the gate, rendering it unusable. In current 90 nm devices, these oxides are only about 20 atoms thick. In 45 nm technology, this thickness is expected to be below 10 atoms. Thus, small amounts of manufacturing variation in the gate oxide can lead to currents penetrating the gate, rendering the device unusable. This problem is compounded by the immense complexity of current designs, which may make it more difficult to test for defects during manufacturing. Vendors may be forced to either spend more time with parts on the tester, or risk having untested defects escape into the field.